Network on chip.

This project makes a pair of low pin count uni directional bus. It enables the CRC generator to read and write data to memory. The interface of the bus is the following: This network on chip works on 8-bit custom bus protocol. It supports 8 basic packets for transmission. The first bit in the packet…

Floating point adder and multiplier.

Single precision floating point format: 32 bits = 1 sign +  8 exponent + 23 mantissa Maximum range of exponent: -126 to +127 Double precision floating point format: 64 bits = 1 sign + 11 exponent + 52 mantissa Maximum range of exponent: -1022 to +1023 (Range, underflow and overflow of FP numbers will be talked…

HOW TO FIX TIMING PROBLEMS

Introduction: This post presents list of some effective techniques to fix timing relevant issues in the logic design. The reader is expected to have basic knowledge of Hardware logic design. He / she is also expected to have known the Static Timing Analysis, since this paper majorly emphasizes on remedies to fix the timing problems of…

I2C and SPI (baby buses)

What are the most important benefits of I2C and SPI? Benefits of I2C: Supports multi masters. Uses only two lines. SDA and SCL. Best from physical design POV. Devices can be added or removed easily without affecting the other devices. Upgrading system is easy. Small printed circuit board. Simplified design. Stable communication protocols. SPI doesn’t…

Coverage.

What is a covergroup? How are they used? A covergroup is a user defined type. It is declared once and multiple instances of that type can be created.A covergroup records the number of occurrences of variables defined by the cover points. Example: enum {red, green, blue} color; bit [3:0], pixel_adr, pixel_hue, pixel_offset; covergroup cg @(posedge…

SV rand and randc.

Where are rand and randc passed in an SV code? In a class. What does declaring a variable rand perform? Variables declared with rand keyword are standard random variables in SystemVerilog. Their values are uniformly distributed over their range. Provide example of randomize function. Bus bus = new; bus.randomize(); printf (“Random values in decimal:%d”, bus.data);…

PCI-E.

What are layers in PCI-E? Transaction Layer Data Link Layer Physical Layer What does TLP layer perform? The TLP layer is responsible for the assembly and disassembly of the Transaction Layer Packets (TLPs). The TLPs are used to perform transactions like reads and writes and certain other events. The TLP layer is also responsible for…

Ring Buses.

How does a ring bus work? In a ring bus, a set of devices are connected consecutively in a circular fashion. Each device is connected to next device forming a single pathway for data. Token is passed among the devices. Likewise, the device which wishes to transfer data over the bus must get the token…

AXI, the loveliest bus!

Basic concepts of AXI bus? Separate address/control and data phases. Supports unaligned data transfers. Supports out-of-order data transfers. Permits address to be issued ahead of actual data transfer. VALID and READY provide two way handshake. How are different portions of AXI bus used? AXI Bus defines a burst-based transaction and has 5 transaction channels. There…

AHB Bus. [on chip]

2. How is addressed transmitted on AHB? Before beginning transfer, the master has to achieve bus ownership. Firstly, the master asserts request for the bus. Then, it is granted access by the arbiter. After gaining bus access, the bus master transfers address by driving address and control signals on the bus. 3. How many address…

Important SystemVerilog QnA.

1. Explain the differences between byte, shortint, int, longint, integer and time. How many bits are each? logic – user defined vector size (4-state). integer – 32 bits (4-state). Signed. time – 64 bits (4-state). Unsigned. reg – user defines vector size (4-state). byte – 8 bits (2-state). Signed or ASCII character. shortint – 16…

Rare Verilog QnA.

1. What are ANSI style declarations? How are they used on ports? Input logic [size] name. A port in the module requires direction and datatype to be specified. In the Verilog-2001 the direction and datatype of a port can be combined into one statement. E.g. module counter (input wire clock, output reg counter) 2. How…